SD5000I-2 vishay siliconix document number: 70296 s-02889?rev. j, 21-dec-00 www.vishay.com 1 n-channel lateral dmos fets (available only in extended hi-rel flow)
v (br)ds min (v) v gs(th) max (v) r ds(on) max ( ) c rss max (pf) t on max (ns) 20 1.5 70 @ v gs = 5 v 0.5 2
quad spst switch with zener input protection low interelectrode capacitance and leakage ultra-high speed switching?t on : 1 ns ultra-low reverse capacitance: 0.2 pf low guaranteed r ds @ 5 v low turn-on threshold voltage high-speed system performance low insertion loss at high frequencies low transfer signal loss simple driver requirement single supply operation fast analog switch fast sample-and-holds pixel-rate switching video switch multiplexer dac deglitchers high-speed driver the SD5000I-2 monolithic switch features four individual double-diffused enhancement-mode mosfets built on a common substrate. this bidirectional device provides low on-resistance and low interelectrode capacitances to minimize insertion loss and crosstalk. built on vishay siliconix? proprietary dmos process, the SD5000I-2 ut ilizes lateral construction to achieve low capacitance and ultra-fast switching speeds. for manufacturing reliability, these devices feature poly-silicon gates protected by zener diodes. the sd5000i is available only in the ??2? extended hi-rel flow. the vishay siliconix ??2? flow complies with the requirements of mil-prf-19500 for jantx discrete devices. s 2 s 1 substrate nc g 2 g 1 d 2 d 1 d 3 g 3 s 3 d 4 g 4 s 4 dual-in-line sidebraze top view 11 12 13 14 2 3 4 1 8 9 10 5 6 7 applications information?see applications note an502
SD5000I-2 vishay siliconix www.vishay.com 2 document number: 70296 s-02889 ? rev. j, 21-dec-00
gate-drain, gate-source voltage +30 v/ ? 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . gate-substrate voltage +30 v/ ? 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . drain-source voltage 20 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . drain-source-substrate voltage 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . drain current 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature ( 1 / 16 ? from case for 10 seconds) 300 c . . . . . . . . . . . . . . storage temperature ? 65 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature ? 55 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . power dissipation a, b : (package) 500 mw . . . . . . . . . . . . . . . . . . . . . . . . . . (each device) 300 mw . . . . . . . . . . . . . . . . . . . . . . . notes: a. derate 4 mw/ c above 25 c
limits parameter symbol b test conditions b min typ c max unit static drain-source breakdown voltage v (br)ds v gs = v bs = ? 5 v, i d = 10 na 20 30 source-drain breakdown voltage v (br)sd v gd = v bd = ? 5 v, i s = 10 na 20 22 drain-substrate breakdown voltage v (br)dbo v gb = 0 v, i d = 10 na, source open 25 35 v source-substrate breakdown voltage v (br)sbo v gb = 0 v, i s = 10 a, drain open 25 35 v ds = 10 v 0.4 drain-source leakage i ds(off) v gs = v bs = ? 5 v v ds = 15 v 0.7 ds(off) gs bs v ds = 20 v 0.9 10 v sd = 10 v 0.5 na source-drain leakage i sd(off) v gd = v bd = ? 5 v v sd = 15 v 0.8 sd(off) gd bd v sd = 20 v 1 10 gate leakage i gbs v db = v sb = 0 v, v gb = 30v 0.01 100 threshold voltage v gs(th) v ds = v gs , i d = 1 a, v sb = 0 v 0.1 0.8 1.5 v v gs = 5 v 58 70 v gs = 10 v 38 drain-source on-resistance r ds(on) v sb = 0 v i = 1 ma v gs = 15 v 30 i d = 1 ma v gs = 20 v 26 resistance match r ds(on) v gs = 5 v 1 5 dynamic forward transconductance g fs v ds = 10 v, v sb = 0 v, i d = 20 ma, f = 1 khz 10 12 ms gate-node capacitance c (gs+gd+gb) 2.5 3.5 drain-node capacitance c (gd+db) v ds = 10 v, f = 1 mhz 2.0 3 source-node capacitance c (gs+sb) v ds = 10 v, f = 1 mhz v gs = v bs = ? 15 v 3.7 5 pf reverse transfer capacitance c rss 0.2 0.5 crosstalk f= 3 khz ? 107 db switching t d(on) 0.5 1 turn-on time t r v sb = 5 v, v in 0 to 5 v, r g = 25 0.6 1 t d(off) v sb = 5 v, v in 0 to 5 v, r g = 25 v dd = 5 v, r l = 680 2 ns turn-off time t f 6 notes: a. t a = 25 c unless otherwise noted. dmca b. b is is the body (substrate) and v (br) is breakdown. c. typical values are for design aid only, not guaranteed nor subject to production testing.
SD5000I-2 vishay siliconix document number: 70296 s-02889 ? rev. j, 21-dec-00 www.vishay.com 3 on-resistance vs. t emperature on-resistance vs. gate-source voltage common-source forward transconductance vs. drain current 300 04812 20 240 180 60 0 16 120 5 v 10 v 1 100 20 16 12 8 4 0 10 25 c v ds = 15 v v bs = 0 v t a = 55 c 125 c 100 ? 60 60 20 ? 20 100 140 80 60 40 20 0 t a ? temperature ( c) i d ? drain current (ma) leakage current vs. applied voltage applied voltage (v) 020 10 na 1 na 100 pa 10 pa 1 pa leakage 4 8 12 16 v gs = 4 v i gss (diode) i d(off) i sbo i s(off) id (off) @ vgs = vbg = ? 5 v is(off) @ vgd = vbd = ? 5v isbo @ vgb = 0 v, drain open i d = 5 ma, v bs = 0 v v gs = 5 v 15 v 10 v 20 v g fs ? forward transconductance (ms) v sb ? source-substrate breakdown voltage (v) ? on-resistance ( r ds(on) ) ? on-resistance ( r ds(on) ) threshold voltage vs. substrate-source voltage leakage current vs. t emperature 5 0 ? 4 ? 20 4 3 2 1 0 h l v gs = v ds = v th i d = 1 ma t a = 25 c 100 10 1 25 50 75 100 125 i gss (diode) t a ? temperature ( c) ? 8 ? 12 ? 16 ? gate-source threshold voltage (v) v gs(th) i d(off) @ v gs = v bs = ? 5 v, v ds = 10 v i s(off) @ v gd = v bd = ? 5 v, v sd = 10 v i gss @ v gs = 10 v i sbo @ v sb = 10 v drain open leakage (na) i sbo i d(off) i s(off) v bs ? body-source voltage (v)
SD5000I-2 vishay siliconix www.vishay.com 4 document number: 70296 s-02889 ? rev. j, 21-dec-00 body leakage current vs. drain-body voltage 01216 8 420 ? body leakage i b v bs ? body-source voltage (v) input admittance forward admittance capacitance vs. gate-source v oltage 10 04 20 8 6 4 2 0 v ds = 10 v, f = 1 mhz v gs = v bs capacitance (pf) 100 10 1 0.1 100 1000 b is g is (ms) v ds = 10 v i d = 10 ma t a = 25 c 100 10 1 0.1 100 1000 (ms) v ds = 10 v i d = 10 ma t a = 25 c v gs ? gate-source voltage (v) f ? frequency (mhz) f ? frequency (mhz) 81216 200 500 200 500 i d = 13 ma 1 ma 100 a 100 na 1 na 100 pa 1 pa 10 a 1 a 10 na 10 pa g fs ? b fs c (gs+sb) c (gs+gd+gb) c (gd+db) c (dg) reverse admittance output admittance 1 0.1 0.01 0.001 100 1000 (ms) v ds = 10 v i d = 10 ma t a = 25 c 100 10 1 0.1 100 1000 (ms) v ds = 10 v i d = 10 ma t a = 25 c f ? frequency (mhz) f ? frequency (mhz) 200 500 200 500 b rs +g rg ? g rg b og g og
SD5000I-2 vishay siliconix document number: 70296 s-02889 ? rev. j, 21-dec-00 www.vishay.com 5 output conductance vs. drain current switching characteristics output characteristics 700 600 500 0 01 7 400 300 200 100 256 t f ? fall time (ns) r l ( 50 04 20 40 30 20 10 0 v bs = 0 v t a = 25 c 1.0 020 4 0.8 0.6 0.4 0.2 0 v bs = 0 v f = 1 khz v ds ? drain-source voltage (v) i d ? drain current (ma) ? drain current (ma) i d 81216 81216 threshold v oltage vs. t emperature 5 ? 60 60 100 20 ? 20 140 4 3 2 1 0 t a ? temperature ( c) 4 v 3 v 2 v v gs = 5 v g os ? output conductance (ms) ? gate-source threshold voltage (v) v gs(th) v ds = 5 v 10 v 15 v v gs = v ds = v th i d = 1 ma ? 5 v ? 1 v ? 0.5 v 0 v v bs = ? 10 v )
510 r l 51 v in to scope +v dd v out to scope 0 v 50% 10% 90% t d(on) t d(off) t r t f +5 v 0 v +v dd v in v out input pulse: td, tr < 1 ns pulse width: 100 ns rep rate: 1 mhz sampling scope tr < 360 ps rin = 1 m cin = 2 pf bw = 500 mhz 50%
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